This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-332232, filed on Oct. 30, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and arrangement of wirings of the semiconductor memory device.
2. Related Background Art
FIG. 4 is a plane layout view of a conventional semiconductor memory device. The semiconductor memory device of FIG. 4 arranges a plurality of sections obtained by dividing a cell array in order to realize a reduction of power consumption and high speed operation. Wirings of control signals supplied to each section are arranged into a wiring area 5 between the sections arranged in line in Y direction.
Each section is provided with a control circuit for reading and writing cell groups in the section. The control circuit reads and writes the cell groups based on various control signals inputted from outside only when a section selection signal is valid.
As capacity of the memory increases, the number of the sections in a chip is also prone to increase. As the number of the sections increases, the number of the control signals also increases, and the wiring area for the control signals also increases. Accordingly, the ratio that the wiring area of the control signals in the entire area of the chip occupies increases, and fabrication cost rises.
Furthermore, as the number of the divided sections increases, there is a problem in which power consumption increases, because the number of the selected main word lines increases. For example, in FIG. 4, the same row address is inputted to a main row decoder A and a main row decoder B. The main word lines driven by these row addresses are different from a section xe2x80x9caxe2x80x9d connected to the main row decoder A and a section xe2x80x9cbxe2x80x9d connected to the main row decoder B. For example, when the cell in the section xe2x80x9caxe2x80x9d is accessed, it is desirable that only the main row decoder A operates. However, because the row addresses inputted to the main row decoders A and B are the same, the main row decoder operates in vain.
Thus, in the conventional semiconductor memory device, there is a problem in which the decoder and so on corresponding to the section which does not perform read/write operates in vain, and as a result, power consumption may increase.
A semiconductor memory device according one embodiment of the present invention, comprising:
a plurality of blocks arranged in line in a first direction, each block including a plurality of sections each having a cell group obtained by dividing a cell array composed of a plurality of cells and a cell group control circuit which controls read/write for the corresponding cell group and operates independently to each other, said plurality of sections being arranged in line in a second direction;
data lines extending in said second direction and commonly connected to said plurality of sections in the same block, said data lines transferring data for said plurality of sections; and
signal lines passing through said plurality of blocks and extending in said first direction, said signal lines transferring at least one of a control signal which controls read/write for said sections, an address signal which selects said sections, and the other signal transferred to said sections.
Furthermore, a semiconductor memory device according one embodiment of the present invention, comprising: a plurality of blocks arranged in line in a first direction, each block including a plurality of sections each having a cell group obtained by dividing a cell array composed of a plurality of cells and a cell group control circuit which controls read/write for the corresponding cell group and operates independently to each other, said plurality of sections being arranged in line in a second direction; data lines extending on said plurality of blocks arranged in line in said first direction, said data lines transferring data to said sections in said plurality of blocks; and signal lines passing through said plurality of blocks and extending in said first direction, said signal lines transferring at least one of a control signal which controls read/write for said sections, an address signal which selects said sections, and the other signal transferred to said sections.